Labels Milestones
BackDiylc and openscad design ## Mechanical assembly Documentation # ---> KiCad # For PCBs designed using KiCad: https://www.kicad.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 0 Minor layout tweaks Minor layout tweaks Minor layout tweaks merged pull request synth_mages/MK_VCO#5 613d1b6f7e Merge pull request 'pcb_finalization' (#1) from bugfix/10hp into main Merge pull request synth_mages/MK_VCO#5 b554ec2138 Add footprint items for panel holes; separate panel and pcb into different files Fireball/Fireball.kicad_pcb | 7889 Fireball/Fireball.kicad_sch | 4 README.md | 2 | 1N5817 | Schottky diode.
- Vertex 1.378441e+000 4.005100e+000 2.494118e+001 facet normal.
- 4.83492 6.98312 vertex 7.16112.
- Vertex 2.33516 9.82083 0.0491304 facet normal 0.0220531 -0.0969866.