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Back\#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape "Name": "Top Solder Paste.
- -0 -0.995185 -0.0980143 vertex 0.4 3.005 16.275.
- 8VA, 2x Sec, http://www.eratransformers.com/product-detail/20 Trafo Printtrafo.