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LM13700 version to see why Use THT electrolytics, finish SMT layout, try on quentin font for size b1fcba1e78f37669542b35a3e32a5257c5c0240c 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be More SR1 notation bacdac34d747275148c56e8293dc209c2e326fe4 f51b7b97734e404127fa5d5d263acbfd66f116e4 Bring in diylc and openscad design ## Mechanical assembly Documentation # ---> KiCad # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes unplated through holes: merged pull request 'More schematics' (#3) from schematic by Eeschema 5.1.10-88a1d61d58~90~ubuntu20.04.1 **Component Count:** 76 | Refs | Qty | Component | Description | Manufacturer | Part | Vendor | SKU | | L1 | 1 | | Tayda | A-4349 | | | | | J10 | 1 aoKicad | 1 | 1uF | Unpolarized capacitor | | | | R16, R18, R26 | 3 | AudioJack2 | Audio Jack, 2 Poles (Mono / TS *(optional) SIP socket, 2.54 mm, 1x4 | | R21, R22, R23 | 3 | A1M .

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