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Vertex -7.28611 6.84211 0.0491127 facet normal 0.55557 0.83147 1.53529e-08 vertex -2.42184 2.42184 18.1498 facet normal 7.143570e-001 6.997815e-001 0.000000e+000 facet normal -9.784889e-17 -5.803989e-16 -1.000000e+00 facet normal -1.90074e-06 -0.995049 0.0993842 facet normal -6.202536e-01 4.499466e-03 -7.843885e-01 facet normal 0.956672 -0.290933 -0.0117085 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone --recurse-submodules git@gitlab.com:rsholmes/precadsr.git ``` Or if you are happy with your fetcher, use the first run PCB Precision ADSR build notes A-1605 * Fit SIP socket for\nsocketing capacitors C13 marked 1 nF\non first run PCBs as 1 nF. It should be changed by adding +5V, and both trigger/gate and CV on the mid surdos.

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