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Nexperia wafer level chip-size package; 15 bumps (6-3-6), 2.37x1.17mm, 15 Ball, 6x3 Layout, 0.4mm Pitch, http://www.st.com/content/ccc/resource/technical/document/technical_note/92/30/3c/a1/4c/bb/43/6f/DM00103228.pdf/files/DM00103228.pdf/jcr:content/translations/en.DM00103228.pdf pSemi CSP-16 1.64x2.04x0.285mm (http://www.psemi.com/pdf/datasheets/pe29101ds.pdf, http://www.psemi.com/pdf/app_notes/an77.pdf UFD Package, 4-Lead Plastic Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/84299/vor1142b4.pdf SSO Stretched SO SOIC 2.54 8-Lead Plastic DFN (2mm x 2mm) (see Linear Technology DFN_18_05-08-1778.pdf DFN20, 6x5, 0.5P; CASE 505AB (see ON Semiconductor 932BB.PDF 144-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf QFN Microchip 8E 16 QFN, 44 Pin, dual row male, vertical entry connector harwin ltek M80 Harwin LTek.

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