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V1 front panel design and includes 2.5mm centerward shift for input and output jacks bottom_row = v_margin + 12; row_1 = v_margin+12; row_2 = row_1 + vertical_space/7; row_3 = row_2 + vertical_space/7; row_5 = working_increment*4 + out_row_1; out_row_7 = working_increment*6 + out_row_1; out_row_6 = out_working_increment*5 + out_row_1; out_row_3 = out_working_increment*2 + out_row_1; out_row_6 = out_working_increment*5 + out_row_1; out_row_3 = out_working_increment*2 + out_row_1; out_row_6 = out_working_increment*5 + out_row_1; out_row_6 = out_working_increment*5 + out_row_1; out_row_6 = out_working_increment*5 + out_row_1; //special-case the knob spacing on the https://www.onsemi.com/pub/Collateral/NCP115-D.PDF Panasonic HQFN-16, 4x4x0.85mm (https://industrial.panasonic.com/content/data/SC/ds/ds7/c0/PKG_HQFN016-A-0404XZL_EN.pdf Panasonic HSON-8, 8x8x1.25mm (https://industrial.panasonic.com/content/data/SC/ds/ds7/c0/PKG_HSON008-A-0808XXI_EN.pdf QFN, 12 Pin (https://www.nxp.com/docs/en/data-sheet/MMZ09332B.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py TSOP-I, 40 Pin (JEDEC MO-153 Var EB https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator ipc_noLead_generator.py DDB Package; 10-Lead Plastic Dual Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [LFCSP]; (see https://www.intersil.com/content/dam/Intersil/documents/l72_/l72.10x10c.pdf LFCSP VQ, 48 pin, exposed pad, thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator Mounting Hardware, inside through hole 3.3mm, height.

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