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Toll thermal vias in pads, 6 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 44 Pin (JEDEC MO-153 Var JB https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator Hirose DF11 through hole, DF11-8DP-2DSA, 4.

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