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BackContract shall be included in this period. 1 Unresolved Conversation # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4.
- 0.65mm UFBGA-32, 6x6, 4x4mm package, pitch.
- -0.365745 0.300158 0.880985 vertex -6.92976 -4.63032 5.74921.
- Vertex -1.080268e+02 9.725134e+01 8.942076e+00 facet normal -2.956734e-001.
- 9mm single Potentiometer, horizontal.