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BackTemporary files fp-info-cache # Autorouter files (exported from Eeschema) *.net # Autorouter files (exported from Pcbnew) *.dsn *.ses New KiCad version; non Al panel Gerbers # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Latest commits for file Schematics/SynthMages.pretty/C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP.kicad_mod (grid_origin -1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer B.SilkS" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 10:22:31 2021 e6b834b08c Fix floating pin for op amp Fix floating pin for op amp style (thickness 0.15) (arrow_length 1.27) (text_position_mode 0) (extension_height 0.58642) (extension_offset 0) keep_text_aligned (text "Kassu used 1 µF \npolyester film looks much \nbetter. Low-Power, Quad-Operational Amplifiers, DIP-14/SOIC-14/SSOP-14
- 0.187549 -0.0570715 0.980596 vertex 0.180748 7.38561 6.88312.
- Chilisin, BMRx00050512-B, 5.4x5.2x1.2mm, https://www.chilisin.com/upload/media/product/power/file/BMRx_Series.pdf Inductor, Chilisin, BMRF00101040, 11.6x10.1x4.0mm.
- DPDT, double coil latching surface mount PLCC.
- -6.18898 6.0001 facet normal.
- 9.722114e-01 -2.341047e-01 2.836258e-04 vertex -1.043276e+02.