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Temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix sr2 blue 531ebcae92ad8ad00635060e3583259ee13cc12b Add html test version b22080a808 More experimentation with panel alignment before printing 9a2ab6dc7f initial notes for v1 front panel 24ca7abc85 Added schmancy pcb for v2 front panel b77534e3fc83cf3f21d8c938a2ebb93ca539acd3 updated README.md updated README.md updated C14 footprint, traces, groundplane updated C14 footprint, traces, groundplane updated C14 footprint, traces, groundplane 82024e96c9b263a83b6caf715e8607e9cf1b7d77 updated README.md README.md | 8 | 1N4148 .

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