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For precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: merged pull request synth_mages/MK_SEQ#2 Added schmancy pcb for v2 front panel design and includes 2.5mm centerward shift for input and send reset to clk_inh to stop progressing .

/arrasta/commit/d9153c70802a10d2fe554f80f1a497b409aac630">d9153c70802a10d2fe554f80f1a497b409aac630 4675f71e05fc19d3608ee6e5061bbe79ae432fb7

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