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Back*.dsn *.kicad_pcb-bak *.kicad_sch-bak *-backups *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: unplated through holes.
- Length 16.51mm width 11.43mm.
- Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel.drl create mode 100644.
- Vertex 5.093810e+000 -2.072080e+000 2.480400e+001 facet normal -0.262789 -0.392071.
- 7.5439 facet normal -7.070898e-001 -4.467160e-003 7.071097e-001 vertex -5.103497e+000.