Labels Milestones
BackPlacement (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" (condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == 'track'" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Minor layout tweaks Minor layout tweaks From c6e6a61475df01d4832847208a59070c5a40c498 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix sr2 blue 531ebcae92ad8ad00635060e3583259ee13cc12b d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Start of LM13700 version to see why Use THT electrolytics, finish SMT layout, try on quentin font for size From d8deca9307af08e321f2f6168a97d7f0d7734956 Mon Sep 17 00:00:00 2001 Subject: [PATCH 10/18] More tweaks after pro review Apply jlcpcb's design rules, small fixes for those.