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Would make for 7 wires to run, so maybe not. It works this way. "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.25, "via_diameter": 0.8, "via_drill": 0.4, More tweaks after pro review "design_settings": { "defaults": { PCB initial layout, no traces }, Add ground fills, fix some clearance issues, make all power traces large Fireball/Fireball.kicad_pro | 4 .../Unseen Servant/Unseen Servant.kicad_sch | 26 .../precadsr-panel-CmtUser.gbr | 209 .../precadsr-panel-CuBottom.gbl | 970 .../precadsr-panel-EdgeCuts.gm1 | 26 .../precadsr_panel_al-F_Cu.gbr | 15 .../precadsr-panel-SilkBottom.gbo | 799 .../precadsr-panel-drl_map.pdf | Bin 0 -> 147621 bytes Images/loop.png | Bin 0.

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