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Issues, make all power traces large "rules": { PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces }, More tweaks after pro review 19116ba39d Apply jlcpcb's design rules, small fixes for those Fireball/Fireball.kicad_pro | 93 Fireball/Fireball.kicad_sch | 64 Fireball/fp-info-cache | 23 (format (units 3) (units_format 1) (precision 4 style (thickness 0.1) (arrow_length 1.27) (text_position_mode 0) (extension_height 0.58642) (extension_offset 0.

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