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BIN Panels/title_test.stl Normal file View File 3D Printing/Cases/Eurorack 2-Row/eurorack_2row_power_supply_base.stl Executable file View File 3D Printing/AD&D 1e spell names in Filmoscope Quentin/PRISMATIC SPHERE.png Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x04_P2.54mm_Vertical.kicad_mod Normal file Unescape ## Gated ADSR operation Whatever appears on the cylindrical part of the first part Binary files a/3D Printing/Panels/HOLD PORTAL.png create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_RA6020F_Single_Slide.kicad_mod delete mode 100644 Hardware/PCB/precadsr/potsetc.kicad_sch delete mode 100644 3D Printing/Panels/HOLD PORTAL.png | Bin 0 -> 43300 bytes Panels/FireballSpell_Large_bw.xcf | Bin 0 -> 70584 bytes 3D Printing/Rails/36hp_outie.stl create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Push_button_A-5050.kicad_mod create mode 100644 Images/PXL_20210831_002553634.jpg Latest commits for file SR 1.pdf | Bin 0 -> 90091 bytes Latest commits for file Panels/luther_triangle_vco_quentin_v4.scad Replaced accidentally dropped Fine tuning hole. Aa68d7a21d Am totally not using git correctly ec09111f77 Futura BT font files 4f2a34f676 's take on FIREBALL VCO using AD&D 1e MM, PHB, and DMG used Futura typeface. Panels/Font files/Futura XBlk BT.ttf create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/MountingHole_3.2mm_M3.kicad_mod delete mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_LED_Hole.kicad_mod delete mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel-cache.lib delete mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Jack_Hole_NPTH.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/D_DO-35_SOD27_P7.62mm_Horizontal.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x10_P2.54mm_Vertical.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/C_Rect_L7.2mm_W2.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2.kicad_mod create mode 100644 Panels/Font files/Quentincaps.ttf create mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel.pretty/precadsr-panel-art.kicad_mod create mode 100644 Images/IMG_6753.JPG create mode 100644 Schematics/OttosIrresistableDance/OttosIrresistableDance.kicad_pcb create mode 100644 Hardware/PCB/precadsr/precadsr.cmp create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Perf_Board_Hole.kicad_mod delete mode 100644 Panels/Futura XBlk BT.ttf | Bin 11692 -> 0 bytes From 8a9583e7df3009c52174c16ce501729b9c90d7ac Mon Sep 17 00:00:00 2001 Subject: [PATCH] Am totally not using git correctly From 4fd9d8b7bf20541267f941aa2eacb4afbb30ba6a Mon Sep 17 00:00:00 2001 Subject: [PATCH 09/13] Notes from debugging More notes C10, C14 too small for a single 1 mm² wires, basic insulation, conductor diameter 0.48mm, outer diameter.

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