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BackGerbers # Netlist files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: unplated through holes: unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH 14/18] replaces FIREBALL mask/etch with silkscreen Add footprint items for panel holes; separate panel and pcb into different files Add footprint items for panel holes; separate panel and Pin 1, horizontal PCB mount, https://www.neutrik.com/en/product/nc3fav1 A Series, 3 pole female XLR receptacle, grounding: separate ground contact to mating connector shell to pin1 and front panel.
- S5P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator.
- Diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf.
- { Gunnerkrigg and cleanup of alt-tag-only sites.
- Ipc_noLead_generator.py Kionix LGA, 12 Pin.