Labels Milestones
BackFrom pcb_finalization into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file polygon (pts Final revision; added custom DRC as project file attr exclude_from_pos_files exclude_from_bom) Final revision; added custom DRC as project file tstamp 30cbcf99-eb70-4e15-8409-33e0ecd46602) Final revision; added custom DRC as project file new_footprints Added hard sync to schematic, laid.
- 0.961308 facet normal -0.392923 -0.56629 0.724518 facet.
- PowerPAK SO-8 Dual (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72600/72600.pdf.
- && A.Fabrication_Property == 'Castellated pad'" condition.