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BackHoles - these gaps reduce heat conduction during soldering ground plane Updates from real TL0x4s re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md 5040873587dbb57684343269abab88d35cf7124b more fixes more fixes glide fix d9235591732ea49a85db49010f2aaf63f936f2b3 re-re-remove the mysterious extra trace Binary files /dev/null and b/Images/PXL_20210831_004139245.jpg differ Images/befaco_vcadsr.png Normal file View File 3D Printing/Jigs/eurorack_test_jig_150mm.stl Executable file View File 3D Printing/AD&D 1e spell names rendered as raster using Filmoscope Quentin typeface Created by editing arbitrary text at 200-size from: https://www.myfonts.com/collections/quentin-font-urw?tab=individualStyles 3D Printing/Panels/BLADE BARRIER.png and /dev/null differ Latest commits for file Panels/title_test.stl STLs, 10hp version, others schematics width_mm=60; height=10; More experimentation with panel alignment before printing Add notes about wiring SW15 cross-board 9360e76802 Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops Compare 27 commits » created pull request 'Fix rail clearance issues, make all power traces large Add ground fills, fix some clearance issues, make all power traces large tracks the ratsnest and compactifies the power subsystem 6f5ee76aea5e7cdfb79e86a703d20d48842d1955 adds front panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane on only one side //calculated x value of exact middle of panel after deducting left/right sub-panels slider_center.
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