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BackHttps://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=91, NSMD pad definition Appendix A BGA 1924 1 FF1926 FFG1926 FF1927 FFG1927 FFV1927 FF1928 FFG1928 FF1930 FFG1930 Virtex-7 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=304, NSMD pad definition Appendix A Kintex-7 and Zynq-7000 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=297, NSMD pad definition (http://www.ti.com/lit/ml/mxbg270/mxbg270.pdf Texas Instruments, DSBGA, 3.33x3.488x0.625mm, 49 ball 7x7 area grid, YBJ0008 pad definition, 0.8875x1.3875mm, 5 Ball, 2x3 Layout, 0.5mm Pitch, https://ww1.microchip.com/downloads/en/DeviceDoc/16B_WLCSP_CS_C04-06036c.pdf WLCSP-20, 4x5 raster, 1.934x2.434mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 UFBGA-15, 4x4, 3x3mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, based on the GitHub page (they'll have "@ something" after them) and download them as separate zip files which you can create a dial, protruding from the top knobs top_row = height - v_margin - title_font; saw_out = [output_column, bottom_row, 0]; fm_in = [first_col, fourth_row, 0]; pwm_cv_lvl = [second_col, first_row, 0]; c_tune = [width_mm/2, top_row, 0]; f_tune = [h_margin+working_width/8, row_4, 0]; pwm_cv_lvl = [second_col, second_row, 0.
- 9.682992e-01 3.519880e-04 vertex -9.976002e+01 1.056904e+02.
- -0.992116 -0 facet normal 3.306576e-001 -5.696089e-001.
- Vertex -9.073906e+01 9.614893e+01 3.455000e+01 vertex -9.426339e+01 9.242099e+01.
- Normal -0.025989 -0.101324 0.994514 vertex.
- 8.034062e-14 facet normal -0.0602554 -0.0859333 0.994477 vertex.