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Vertex -9.046766e+01 1.008749e+02 1.032976e+01 facet normal -0.309927 0.7481 0.586763 vertex 3.2761 2.20578 19.9 facet normal 0.84429 -0.451284 0.288993 vertex -7.46009 -4.98467 4.79464 facet normal -0.0433039 -0.0700998 0.9966 vertex 0.0206242 7.34599 6.86125 facet normal -0.231109 0.464148 0.855076 vertex -5.35776 -4.75988 6.96188 vertex -7.07772 0.359534 6.95295 facet normal 0.442582 0.106257 0.890411 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md) How to use Git repository From 40ce306867b3d353457e134a232ee65f5767bece Mon Sep 17 00:00:00 2001 Subject: [PATCH] Put title box in PDF export Merge pull request 'Put title box in PDF export 45cf8c00cd Merge pull request 'Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces }, More tweaks after pro review "extra_units": "error", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", "lib_symbol_issues": "warning", More tweaks after pro review Fireball/Fireball.kicad_pro | 19 .../SolderWirePad_1x01_Drill1mm.kicad_mod | 19 }, From 7022ad9ddb43c592e11528a5ae21edf443c088e4 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops Compare 27 commits » created pull request 'pcb_finalization' (#1) from bugfix/10hp into main ... Add jlc constraints DRC; replace order number text Add jlc constraints DRC; replace order number text.

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