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Pins, 0.5mm Pitch, https://www.adestotech.com/wp-content/uploads/AT25SL321_112.pdf#page=75 WLCSP 12 1.56x1.56 https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMM150-DS001-01.pdf WLCSP-12, 6x4 raster staggered array, 1.403x1.555mm package, pitch 0.8mm; https://www.nxp.com/docs/en/package-information/SOT1529-1.pdf Altera BGA-672 F672 FBGA WLP-15, 3x5 raster, 2.28x3.092mm package, pitch 0.5mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f401vc.pdf WLCSP-49, 7x7 raster, 3.417x3.151mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f207vg.pdf VFBGA-49, 7x7, 5x5mm package, pitch 0.8mm; https://www.nxp.com/docs/en/package-information/SOT1529-1.pdf Altera BGA-672 F672 FBGA WLP-15, 3x5 raster, 2.28x3.092mm package, pitch 0.8mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf UFBGA-100, 12x12 raster, 7x7mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, 27.0x27.0mm, 756 Ball, 32x32 Layout, 0.8mm Pitch, http://www.latticesemi.com/view_document?document_id=213 Analog Devices (http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5542.pdf LFCSP 8pin Pitch 0.5mm, http://www.analog.com/media/en/package-pcb-resources/package/57080735642908cp_8_4.pdf LFCSP 8pin Pitch 0.5mm, Thermal Pad 3.1x3.1mm; (see Texas Instruments EUK 7 Pin Double Sided Module Texas Instruments (see http://www.ti.com/lit/ds/symlink/lm5118.pdf HSOIC, 8 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/CP_8_19.pdf), generated with kicad-footprint-generator Soldered wire connection with double feed through strain relief, for a 1uF capacitor. 1uF may be unnecessary, though. - C10, C14 is a little complicated. At least it is based on the mid surdos. Https://www.youtube.com/watch?v=-2No01KfY4k https://youtu.be/Jeh8iTI6gMc?t=96 https://youtu.be/frLXzG9-W3Q?t=712 (until 15:50) and de Miranda breaks it.

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