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BackB.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] learns about gitignore and git rm --cache 269f3bf9f9 power word stun initial commit by power word stun initial commit by power word stun initial commit by Synth Mages Power Word Stun.kicad_pcb alternate "" input line From 5505000471ab249f70d985a8f814bce077fb47b2 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Added hard sync to schematic, laid out PCB with exploratory 8hp layout 2bd01a1ff2d30ca3cff647bbf3b80645437cc07c Add schematic, start on PCB sandwich, making some final-ish decisions about connecting to front panel 24ca7abc85681936397a2802c8155420fcaf679c Added schmancy pcb for v1 build pushed tag v1.0 to synth_mages/MK_SEQ released Prototype Version 1.0 at synth_mages/MK_SEQ pushed tag v1.0 to synth_mages/MK_VCO Forget (and ignore) fp-info-cache file as it is .gitignore | 1 | Synth_power_2x5 | 2x5 pin shrouded header 2.54 mm spacing"/>