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Vertex -4.02975 3.69322 21.8414 facet normal -0.0822024 0.0560446 0.995039 facet normal 0.991524 -0.109217 0.0703647 facet normal -0.273132 0.564081 0.779238 facet normal -0.124364 -0.485049 0.865599 vertex -4.56563 -5.2499 7.05523 facet normal -0.575169 -0.528289 0.624573 facet normal 0.703593 -0.707111 0.0703601 facet normal 0.695391 0.464642 -0.548215 vertex -2.58025 -1.95159 18.574 vertex -2.37646 -2.37646 18.4724 vertex 0.4 2.86172 18.9065 facet normal 9.969208e-01 -2.027510e-03 7.838883e-02 facet normal 0.491338 -0.598691 0.632579 vertex 6.18591 6.18591 5.33536 facet normal 0.137354 0.452791 0.880973 facet normal -0.309855 -0.748097 0.586806 facet normal -0.23112 0.46415 0.855072 facet normal 0.607324 0.740028 0.288991 facet normal -0.916106 0.277896 0.289006 facet normal -3.776893e-15 -4.049106e-15 1.000000e+00 facet normal -0.288986 0.749614 0.595454 facet normal -0.0169529 0.828691 0.559449 facet normal 6.820989e-01 7.312599e-01 1.425847e-04 vertex -9.262627e+01 1.042954e+02 4.255000e+01 facet normal -0.634386 0.773016 0 facet normal 4.330088e-01 1.474605e-03 -9.013885e-01 facet normal 0.591985 -0.205725 0.77925 vertex -6.59163 -0.162663 7.16505 facet normal 3.630980e-01 6.368435e-03 9.317292e-01 facet normal -0.0906197 -0.920082 0.381101 facet normal 0.284746 -0.909897 0.301674 vertex 6.4137 0.394998 7.51797 vertex 0.410784 -6.35181 7.71954 vertex -6.29114 -0.209414 7.71246 vertex -6.4137 -0.394998 7.51797 facet normal -2.096582e-001 -3.669018e-001 9.063259e-001 facet normal 0.782842 0.468344 0.40965 facet normal 6.62301e-05 -0.115847 -0.993267 facet normal 0.0222629 -0.0969963 0.995036 vertex 2.47665 7.61209 19.9494 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone git@gitlab.com:rsholmes/precadsr.git git submodule init git submodule update ``` ``` git clone git@github.com:holmesrichards/precadsr.git New KiCad version; non Al panel Gerbers # Netlist files (exported from Pcbnew *.ses # Exported BOM files *.xml *.csv # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: merged pull request 'Put title box in PDF export Schematics/Fireball_VCO.pdf.

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