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(j1/j13 // gate out (j4/j10 // clock in (j2/j11) // casc out (j14/j15 // reset/casc in (j1/j13 // gate out (j4/j10) // clock out (j5/j12 // glide atten (rv15 // 13 SPDT switches: // 10 LEDs 3 sockets 6 sockets Potentiometers: One potentiometer per step, to set clock rate // Top radius of the terms of the indenting spheres, measured from the other leg of the shaft on the front panel. This can be the same size as traces - vias connect through the PCB is used. C1 is too small; need more than 100k to get 1:1 between schematic and PCB, no warnings More work finding space for everything, lining things up more Binary files /dev/null and b/Panels/FireballSpellVertSmaller.png differ Binary files /dev/null and b/Panels/FireballSpellVertVerySmall.png differ Binary files /dev/null and b/3D Printing/Panels/HOLD PORTAL.png differ Binary files /dev/null and b/Examples/EG_MANUAL.pdf differ Binary files /dev/null and b/Panels/futura light bt.ttf | Bin 0 -> 36336 bytes create mode 100644 3D Printing/Rails/18hp_outie.stl | Bin 0 -> 92229 bytes Panels/FireballSpellSmall.png | Bin 0 -> 580484 bytes .../Panels/Radio_shaek_standoff_padded_2.stl | Bin 77965 -> 0 bytes c58f541d7e Upload files to '3D Printing/Panels/AD&D 1e spell names on narrower widths. The first two groups should be possible, too .

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