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Back(j2/j11 // casc out (j14/j15 // reset/casc in (j1/j13 // gate out // RESET in // GATE out - could be other values, ceramic may work, test debouncing. Maybe enlarge footprint if needed. - Resistor footprint could stand to be more robust and easier to adjust CV output range, switch between 5v and 2.5v max. One per step, to enable/disable gate per step. (10 One potentiometer for internal clock signal (possibly external). Commonly called a "Baby 8". Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF' (#2) from schematic into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/3 More schematics Schematics/Luthers_Perfboard.pdf | Bin 0 -> 36336 bytes create mode 100644 Synth Mages Power Word Stun-backups History 269f3bf9f9 power word stun initial commit by Synth Mages Power Word Stun.kicad_pcb group "" (id efdac9a8-63a2-4056-9007-59528f4494a3 Username Email Address Password Confirm Password CAPTCHA Already have an account? Sign in now! Main synth_tools/Schematics/SynthMages.pretty/SOCKET_3_PIN_HEADER_NORMAL.kicad_mod 45 lines C1 is too small for film; is film needed? More notes Schematics/schematic_bugs_v1.txt | 2 .../OttosIrresistableDance.kicad_sch | 5 | 2N3904 | 0.2A Ic, 40V Vce, Small Signal NPN Transistor, TO-92"/>