X="5.475" y="5.15"/> Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= 2dd0b8c0c736720a0b064bbe1304dc9562beb260 Latest commits for file LICENSE 9e7b04561b Add ground fills, fix some clearance issues, make all power traces large From 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Mon Sep 17 00:00:00 2001 Subject: [PATCH] Optional capacitor socket # Temporary files *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: merged pull request synth_mages/MK_VCO#5 Final.
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