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BackB.Cu" "Notes": "Layer B.Cu" "Notes": "Layer F.SilkS" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= 5ff3077e8252367b7eceb0b21b0803904b695d42 Fix sr2 blue Fix sr2 blue 2bd01a1ff2d30ca3cff647bbf3b80645437cc07c start e49f4ab127dc081ee1c77dd21e80d128628a1152 2dd0b8c0c736720a0b064bbe1304dc9562beb260 init c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score caixa_sr1.png | Bin 10724 -> 0 bytes Latest commits for file PSU/psu.diy Add PSU PSU/PSU.md | 5 | 22k | Resistor | | C10.
- -0.55118022,2.5590618 h -0.07874" d="m -4.7244126,1.1417373 v.
- JackHoles, mountHoles=2, hw = holeWidth, ignoreMountHoles=false //mountHoles ought.
- 0.081933 -0.133696 0.98763 facet normal 0.828702 0.0816302 0.553705.
- = row_2 + vertical_space/7; row_7 .