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-2.5 6.7 vertex 2.45196 -0.487725 6.5 vertex -1.38893 2.07867 6.7 vertex -0.487725 -2.45196 6.5 facet normal -0.421013 -0.192217 0.886454 facet normal 0.222395 -0.884723 0.409641 facet normal -8.332533e-02 9.965224e-01 2.477165e-06 vertex -9.778416e+01 1.060829e+02 4.255000e+01 vertex -9.435317e+01 1.041514e+02 4.255000e+01 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md) How to apply CC0 to the last step and output jacks Latest commits for file Schematics/SynthMages.pretty/SLIDE_POT_0547.kicad_mod From ec89d624dcbabc43243d2dcb7078e4434becb7c8 Mon Sep 17 00:00:00 2001 Subject: [PATCH.

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