Labels Milestones
Back*-save.pro *-save.kicad_pcb fp-info-cache # Autorouter files (exported from Eeschema *.net # Autorouter files (exported from Pcbnew # Exported BOM files *.xml *.csv # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: merged pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Merge pull request 'Put title box in PDF export Put title box in PDF export' (#4) from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main Merge pull request 'More schematics' (#3) from schematic into main 26b0f01955 Fix for component clearance, panel thickness from printer Binary files a/3D Printing/AD&D 1e spell names in Filmoscope Quentin' d8a7439c05 Upload files to '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/SPIDER CLIMB.png.
- Sockets: // clock out (j5/j12 // glide.
- (4 holes T5 15.200mm 0.5984" (1 hole.
- More minor clearance tweaks Add ground fills.
- -0.682997 -0.618219 0.388999 facet normal.