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Back\#* New KiCad version; non Al panel Gerbers *~ New KiCad version; non Al panel Gerbers # Netlist files (exported from Pcbnew # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main Merge pull request 'Put title box in PDF export Merge pull request 'Fix rail clearance = ~11.675mm, top and bottom boards. Latest commits for file Synth_Manuals/Module Summaries.ods