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Main MK_VCO/Fireball/Fireball_panel.kicad_pcb 11852 lines tstamp 189e5c14-d81a-45a9-b8ba-c69582490088) Final revision; added custom DRC as project file tstamp 6b7d6cc6-a11c-4566-a5f2-ddde4d827642) Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file version 1) #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'track' && B.Type == A.Type" condition "A.Type == 'track' && B.Type == 'track'" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'track'" (condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'track' && B.Type == 'track'" condition "A.Type == 'pad' && B.Type == 'graphic')" # This would override board outline and milled areas # (condition "A.Type == 'via'" (condition "A.Type == 'pad' && B.Type == A.Type" (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" condition "A.Type == 'track' && B.Type == 'graphic')" (condition "A.Type == 'via' && B.Type == 'track'" (condition "A.Type == 'via'" (condition "A.Type == 'track'" condition "A.Type == 'pad' && B.Type == A.Type" condition "A.Type == 'via' && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'track' && B.Type == 'graphic')" # This would override board outline and milled areas # (condition "A.Type == 'pad.

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