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Back"min_copper_edge_clearance": 0.0, PCB initial layout, no traces One SPST switch per step, to enable/disable gate per step. (10 Momentary-normal-off pushbutton to manually reset. More repo cleanup, adopt github .gitignore file f45c980890 Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane 56529bef3a Updates from real TL0x4, fix pots being backwards, tighten up schematic, fit letter instead of the rail + a safety margin // margins from edges v_margin = hole_dist_top*2 + thickness; width_mm = 70.8; // 14HP×5.08mm = 71.12; ES for 14HP is 70.8 c_tune = [width_mm/2 + h_margin, top_row, 0]; f_tune = [h_margin+working_width/8, row_3, 0]; c_tune = [second_col, third_row, 0]; //Fourth row interface placement sync_in = [first_col, third_row, 0]; saw_out = [h_margin .
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