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BackEmacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= 0d3d72c49e606725216a5a9a4217e6c039d5a574 2bb058d5715f395d3571ea05d3008566787a2bdb main MK_SEQ/Schematics/Unseen Servant/Unseen Servant_slider_board_noncanonical.kicad_prl Normal file Unescape Schematics/SynthMages.pretty/PinSocket_1x02_P2.54mm_Vertical.kicad_mod Normal file Unescape // Width of module (HP) width = 14; // [1:1:84] /* [Holes] */ hole_dist_top = 2.5; //mm first_col .
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