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BackTstamp a19ef654-a631-44b9-8b6b-999333495c1b) Final revision; added custom DRC as project file tstamp e90beec6-952b-474b-a043-0f4708c5b9c2) Final revision; added custom DRC as project file attr exclude_from_pos_files exclude_from_bom) Final revision; added custom DRC as project file Final revision; added custom DRC as project file polygon (pts Final revision; added custom DRC as project file ) ) New KiCad version; non Al panel Gerbers # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH 15/18] Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | 10k | Resistor | | | U1 | 1 | 10nF | Film capacitor | | | | | L1 | 1 | 2_pin_Molex_header | 2 .../OttosIrresistableDance.kicad_sch | 5 | 2N3904 | 0.2A Ic, 40V Vce, Small Signal NPN Transistor, TO-92"/>