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Back\#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Minor layout tweaks From 8f3ce8359ba460976b5ffcbe5a92590e33120bbc Mon Sep 17 00:00:00 2001 Subject: [PATCH] More experimentation with panel alignment before printing Messing around with panel alignment before printing 9a2ab6dc7f initial notes for v1 build - C1 is too small; need more than 100k to.
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