3
1
Back

No traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces PCB initial layout, no traces Initial kicad, images, gitignore for kicad backups afea9d5a2c Final revision; added custom DRC as project file tstamp e90beec6-952b-474b-a043-0f4708c5b9c2) Final revision; added custom DRC as project file tstamp 42deceed-4793-4b11-91d8-f336ff75a562) Final revision; added custom DRC as project file version 1) #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'track' && B.Type == 'graphic')" (condition "A.Type == 'via'" condition "A.Type == 'pad' && B.Type == A.Type")) # 4-layer condition "A.Type == 'pad' && B.Type == A.Type" (condition "A.Type == 'via' && B.Type == 'track'" (condition "A.isPlated() && B.Type == 'track'" (condition "A.Type == 'via' && B.Type .

New Pull Request