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Mess From 7022ad9ddb43c592e11528a5ae21edf443c088e4 Mon Sep 17 00:00:00 2001 Subject: [PATCH] checkpoint after roughing out middle PCB ebf8c2dd87 Move LED resistors next to transistors to save on panel wires 2eebdf7ecf Add four more switches/buttons, move LED drivers onto PCB .../Unseen Servant/Unseen Servant.kicad_sch | 1120 From 1ed9d69b418eb6a9322b9893aea438f59933f7f4 Mon Sep 17 00:00:00 2001 Subject: [PATCH] More random files main MK_SEQ/Schematics/Unseen Servant/Unseen Servant_counter_board_noncanonical.kicad_pcb Normal file View File // testing futura vs quentincaps in F6 rendering //font_for_title = default_label_font; title_font_size = 22; label_font_size = 5; height_of_cylinder_indentations = 12; hole_vdist = 44.5; hole_hdist = 65; hole_diameter = 2; left_col = 10 + right_panel_width + thickness, th=1.5); main MK_SEQ/Schematics/Unseen Servant/Unseen Servant_slider_board_noncanonical.kicad_pro Normal file View File VCO_MANUAL_v2.pdf Executable file View File Panels/luther_triangle_vco_quentin_v3_only_art.stl Normal file Unescape Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-F_SilkS.gbr Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-F_Paste.gbr Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-PTH.drl Normal file View File Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-NPTH.drl Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x02_P2.54mm_Vertical.kicad_mod Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/TerminalBlock_Degson_DG301_1x03_P5.00mm_Vertical.kicad_mod Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Wall_wart_A-4118.kicad_mod Normal file View File Images/retrigger.png Normal file View File Images/loop.png Normal file Unescape Schematics/SynthMages.pretty/PinSocket_1x03_P2.54mm_Vertical.kicad_mod Normal file Unescape Hardware/Panel/precadsr_panel.png Normal file View File 3D Printing/Cases/Eurorack Modular Skeleton/CE3_Eurorack_box_v105.3mf Executable file View File 3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels' 5209c5fd76f5cb84bb09be3d7c836a3c6a5d5355 Upload files to 'Panels' From e49f4ab127dc081ee1c77dd21e80d128628a1152 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Image of caxia score d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Start of LM13700 version to see why d9153c70802a10d2fe554f80f1a497b409aac630 sr1 f51b7b97734e404127fa5d5d263acbfd66f116e4 Add schematic, start on PCB sandwich, making some final-ish decisions about connecting to front panel b77534e3fc83cf3f21d8c938a2ebb93ca539acd3 updated README.md updated README.md acf6d57d9f34ce2c424f4c9834d80264fa5ffd89 @circuitlocution.com renamed repository from precadsrprecadsr to synth_mages/MK_VCO merged pull request 'new_footprints' (#5) from new_footprints into main ... Add jlc constraints DRC; replace order number text Add jlc constraints DRC; replace.

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