3
1
Back

Traces "silk_line_width": 0.15, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces Fireball/Fireball.kicad_prl | 2 aoKicad | 1 | 3_pin_Molex_header | 3 From afea9d5a2cf23e2a33a2927086270d4d602f5a2b Mon Sep.

New Pull Request