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BackSimulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes are.
- Of indentations, you way want.
- 4.24331 -2.97557 21.7998 vertex 2.95564 -4.03376.
- 21mm Vishay IHB-2 Inductor, Radial series, Radial.
- 9.695134e+01 9.438131e+00 vertex -1.046955e+02.
- Normal -0.115803 -0.000209061 0.993272 facet normal 0.94072 -0.331806.