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From 3d0ca7fdf6e2ad8d7864221e585c668e46544055 Mon Sep 17 00:00:00 2001 Subject: [PATCH] checkpoint before getting really weird with WireIt A couple more minor clearance tweaks 9e7b04561b Add ground fills, fix some clearance issues, make all power traces large "rules": { PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces }, Add ground fills, fix some clearance issues, make all power traces large Fireball/Fireball.kicad_pro | 8 pin DIP socket | | Tayda | A-1138 | | | | | | | | D 2 pin Molex connector 2.54 mm spacing | Tayda | A-1624 or A-2969 | | | | | | Tayda | A-4349 | | | | | S1 | 1 | 4.7 uF | Polarized capacitor | | ----- | --- | ---- | | J12 | 1 | ICM7555xP | CMOS General Purpose Timer, 555 compatible, PDIP-8 Quad operational amplifier, DIP-14 | | | | Tayda | A-4349 | | R31 | 1 | B10k | Potentiometer | | | | | Tayda | A-3588 | | | | | J6, J10, J11 | 3 | 10uF | Electrolytic capacitor | | | | | R4, R12, R13 | 3 pin Molex header 2.54 mm spacing | Tayda.

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