synth_tools

Back

FH12-36S-0.5SH, 36 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing⟨=en&documentid=0000992393), generated with kicad-footprint-generator Hirose DF12C SMD, DF12C3.0-50DS-0.5V, 50 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator Soldered wire connection with feed through strain relief, for 5 times 1.5 mm² wires, reinforced insulation, conductor diameter 0.65mm, outer diameter 1mm, size source Multi-Contact FLEXI-E 2.5 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator connector wire 0.127sqmm strain-relief Soldered wire connection with feed through strain relief, for 5 mm Small Signal NPN Transistor, TO-92 | | | | | | | C1, C11, C12 | 2 .../Unseen Servant/Unseen Servant.kicad_sch | 647 Latest commits for file PSU/psu.diy Add PSU Add PSU Latest commits for file Panels/title_test_18.stl 0 0 Y N 1 F N DEF SW_Reed SW 0 0 PCM_kikit Tab A symbol representing annotation for tab placement (condition "A.Type == 'track'" condition "A.Type == 'pad' && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'track'" condition "A.Type == 'via' && B.Type == 'graphic')" (condition "A.Type == 'track' && B.Type == A.Type" condition "A.Type == 'via' && B.Type == 'track'" (condition "A.isPlated() && B.Type == A.Type && A.Net == B.Net" (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" (condition "A.Net != B.Net" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')" # This would override board outline and milled areas # (condition "A.Type == 'via' && B.Type == 'track'" (condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 11:11:04 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 Not plated through holes: unplated through holes: .

New Pull Request

Labels Milestones