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0.243768 0.923219 facet normal 0.766813 -0.634148 0.0992721 facet normal -0.26053 0.962898 -0.0703667 vertex -6.01015 -7.7867 1.4831 facet normal 4.395874e-001 -7.536180e-001 4.886950e-001 vertex -3.455805e+000 2.660052e+000 2.484855e+001 facet normal -0.0820856 -0.0820533 -0.993242 vertex -3.08479 4.5363 21.833 vertex -1.05741 7.11568 7.9151 facet normal -0.0729058 0.338907 0.937991 facet normal 0.654317 0.271031 0.705982 vertex 5.3435 -1.85172 19.4867 facet normal -8.244231e-16 -2.375573e-15 -1.000000e+00 facet normal 0.12243 0.987495 0.0993177 facet normal 0.367898 0.00384978 0.929858 vertex 0.303284 7.37107 6.90571 facet normal -0.241804 0.796836 0.553699 facet normal -0.881916 0.471406 0 vertex -5.31736 8.65691 2.19603 facet normal 0.0376662 -0.382434 0.923215 vertex -0.0330347 -8.99675 3.82299 facet normal 0.430898 0.353597 0.830239 facet normal -0.976242 0.096139 0.194186 facet normal -0.370051 0.603866 0.70598 facet normal 5.035290e-001 2.242178e-003 8.639754e-001 facet normal 9.969322e-01 -7.826654e-02 -6.701070e-04 vertex -1.045672e+02 9.852583e+01 1.755000e+01 facet normal -0.634391 0.773012 0 facet normal -0.486762 -0.388502 0.782387 vertex -4.767 -4.767 7.03201 vertex 4.64974 -4.64974 7.16319 facet normal -0.665275 0.392534 0.63508 facet normal 9.106134e-01 1.135808e-03 4.132577e-01 vertex -1.083043e+02 9.725134e+01 5.018543e+00 vertex -1.082465e+02 9.695134e+01 4.891894e+00 facet normal 0.76848 -0.630655 0.108222 facet normal 7.954739e-01 -2.016707e-03 6.059846e-01 facet normal -0.500165 -0.865929 0.00115989 facet normal -1.226499e-001 1.990150e-004 9.924500e-001 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 Experimenting with more panel layout Start of LM13700 version to see why 0d3d72c49e Use THT electrolytics, finish SMT layout, try on quentin font Schematics/Enlarge/Enlarge.kicad_prl | 10 uF tantalum\nMFOS 1, 1+15 electrolytic\n1 uF tanty looks better than EL\n(higher output, less leakage)\nbut only by a little. 1 uf \npolyester film looks much \nbetter. F0 "Pots, switches, misc" plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] checkpoint before getting really weird with WireIt dd8c61c34f A couple more minor clearance tweaks 9e7b04561b Add ground fills, fix some clearance issues, add PCB slot, more options for potentiometer spoke placement' (#1) from bugfix/10hp into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file ad96459571a569a983e452184e49702fe8779c4e Merge pull request synth_mages/MK_VCO#7 * In the above copyright.

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