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BackFile Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-NPTH.drl Normal file View File Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pretty/Bigger_Push_Switch_Hole.kicad_mod Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-PTH.drl Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pro Normal file View File Panels/luther_triangle_vco.scad Executable file Unescape "Name": "Top Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Silk Screen" Hardware/Panel/precadsr-panel/precadsr-panel-cache.lib Normal file View File # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Fireball/Fireball_panel.kicad_dru Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-B_SilkS.gbr Normal file View.
- 0.0808315 0.0820554 0.993344 vertex 5.18289.
- Normal -0.422843 0.331544 0.843375 vertex -5.54018 -4.83492.
- 6.67052 1.15689 20 vertex -2.00861.
- Version fairly simple. - CV out .
- Sagami power inductor, 7.8x7.0x3.5mm.