3
1
Back

HLE-104-02-xxx-DV-BE, 4 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py DFN8 2x2, 0.5P; No exposed pad (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-87/ 12-Lead Plastic DFN (3mm x 3mm) (see Linear Technology DFN_14_05-08-1708.pdf DFN14, 4x4, 0.5P; CASE 505AB (see ON Semiconductor Micro8 (Case846A-02): https://www.onsemi.com/pub/Collateral/846A-02.PDF PSOP44: plastic thin shrink small outline package; 56 leads (see NXP sot054_po.pdf to-92 sc-43 sc-43a sot54 PA33 transistor TO-92 2-pin leads in-line, wide, drill 0.75mm.

New Pull Request