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Href="https://gitea.circuitlocution.com/synth_mages/MK_SEQ/commit/f33ea6a168329cd0061e01c376cbd377f46ddc60">f33ea6a168329cd0061e01c376cbd377f46ddc60 @circuitlocution.com created pull request synth_mages/MK_VCO#1 32ded0979b Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces a3181ad06b Add.

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