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BackTo trigger, gate jack is normalized\nto +12 V, 10 mA -12 V Add html test version b1fcba1e78f37669542b35a3e32a5257c5c0240c 9060b76361734f9abf9a1c676dd9110e9ced917b initial kicad project main MK_SEQ/.gitignore 3 lines Latest commits for file Synth_Manuals/Module Summaries.ods | Bin 0 -> 147621 bytes Images/loop.png | Bin 11692 -> 0 bytes (group "" (id efdac9a8-63a2-4056-9007-59528f4494a3 Username Email Address Password Confirm Password CAPTCHA Already have an account? Sign in now! Main synth_tools/Schematics/SynthMages.pretty/SOCKET_3_PIN_HEADER_NORMAL.kicad_mod 45 lines C1 is too small; need more than 100k to get below 200bpm - C1 is too small for a clock on the mid surdos. .