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Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Minor layout tweaks Based on a decade counter Bergman's 10-step sequencer (up to 10 nF | Unpolarized capacitor | | | | | R109, R111, R113 | 3 create mode 100644 Images/PXL_20210831_000949090.jpg create mode 100644 Schematics/Luthers_Perfboard.pdf From aa68d7a21dc81e7382706897022ddc81b9f5db22 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update readme Update readme Schematics/SEQ_MANUAL_v2.pdf | Bin 26014376 -> 26031216 bytes // PCB holder main MK_VCO/Panels/Font files/futura light bt.ttf | Bin 0 -> 144834 bytes .../Pot_Knobs/pot_knob_two_parts_cap.stl | Bin 0 -> 9479 bytes main MK_VCO/Schematics/MK_VCO_RADIO_SHAEK.diy 5515 lines 2bd01a1ff2 Add schematic, start on PCB Added input resistor for sync; placed everything on PCB with exploratory 8hp layout Add schematic, start on PCB 398c2b234c Checkpoint after tweaking footprints some more, starting over at 14hp Added hard sync to schematic, laid out PCB with exploratory 8hp layout Add schematic, start on PCB Added hard sync to schematic, laid out PCB with exploratory 8hp layout
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