Labels Milestones
BackClearance issues, make all power traces large "rules": { PCB initial layout, no traces }, Add ground fills, fix some clearance issues, make all power traces large tracks the ratsnest and compactifies the power subsystem Checkpoint after tweaking footprints some more, starting over at 14hp cd18ed43dc Added hard sync to schematic, laid out PCB with on-board components hard_sync traces added but maybe won't keep traces added but maybe won't keep Fireball/Fireball.kicad_prl | 4 .../PCB/precadsr_Gerbers/precadsr-job.gbrjob | 2 | 4.7k | Resistor | | | Tayda | A-3588 | | | | | J3, J4, J5 | 3 | A1M | Potentiometer | | | | C3, C4, C5 | 2 | | | | | | | R15, R20, R22 | 3 | 2_pin_Molex_header | 2 | | | Tayda | A-962 | | R30 | 1 | 10nF | Unpolarized capacitor | | | | J7 .
- Next. Something to generate all kinds of.
- (https://www.analog.com/media/en/technical-documentation/data-sheets/436412f.pdf#page=22), generated with kicad-footprint-generator Molex Sabre.