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BackUnescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-PTH.drl Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Align panel to integer pseudo-origin, remove testing text, decrease title label.
- Normal -4.323922e-002 -7.566866e-002 9.961951e-001 vertex -6.585044e-003 6.117642e+000 2.496000e+001.
- 28 pins, through hole M3.
- 3951 Fireball/fp-info-cache | 36.